`include "defines.v"

//rom module
module rom(
    input clk,
    input wire rst,

    input wire[`MemAddrBus] addr_i,    // addr
    output reg[`MemBus] data_o        // read data 

    );

    reg[`MemBus] _rom[0:`MemNum - 1];   

    
    always @ (*) begin
        if (rst == `RstEnable) begin
            data_o = `ZeroWord;
            //初始化寄存器
            _rom[0][`MemBus] = 32'b000001110100_00000_000_00001_0010011;//addi x1 = 0x74 即_rom[29]的地址
            _rom[1][`MemBus] = 32'b000000011000_00000_000_00010_0010011;//addi x2 = 0x18 即_ram[6]的地址
            _rom[2][`MemBus] = 32'b000000000101_00000_000_00011_0010011;//addi x3=n 此处为5
            _rom[3][`MemBus] = 32'b000000000010_00000_000_10011_0010011;//addi x19=2
            _rom[4][`MemBus] = 32'b000000001101_00000_000_00100_0010011;//addi x4=13

            _rom[5][`MemBus] = 32'b000000000001_00000_000_00110_0010011;//addi x6 = i 此处为1
            _rom[6][`MemBus] = 32'b000000000001_00000_000_01010_0010011;//addi x10=1
            _rom[7][`MemBus] = 32'b000000000001_00000_000_10010_0010011;//addi x18=1
            _rom[8][`MemBus] = 32'b000000000010_00000_000_10011_0010011;//addi x19=2
            _rom[9][`MemBus] = 32'b000000000001_00000_000_11101_0010011;//addi x29=a 此处为1
            _rom[10][`MemBus] = 32'b000000000001_00000_000_00101_0010011;//addi x5=b 此处为1
            _rom[12][`MemBus] = 32'b00_0001_0100_00000_010_01010_0000011;//lw x10=_ram[5]=n
        //初始化ram
            _rom[11][`MemBus] = 32'b0000000_00011_00000_010_10100_0100011;//sw _ram[5]=x3=n
        //执行    
            _rom[13][`MemBus] = 32'b0_000000_01010_10010_000_0110_0_1100011;//beq if(x10==x18) jump to _rom[16]
            _rom[14][`MemBus] = 32'b0_000000_01010_10011_000_0100_0_1100011;// beq if(x10==x19)jump to _rom[16]
            _rom[15][`MemBus] = 32'b0_0000000110_0_00000000_11111_1101111;//jal jump to _rom[18]
            _rom[16][`MemBus] = 32'b0000000_10010_00010_010_00000_0100011;//sw _ram[6]=x18=1
            _rom[17][`MemBus] = 32'b000000000000_00001_000_11111_1100111;//jalr jump to _rom[29]
            _rom[18][`MemBus] = 32'b0000000_01010_00110_011_11100_0110011;//sltu if(x6<x10) x28=1 else x28=0
            _rom[19][`MemBus] = 32'b0_000001_00100_00101_000_1110_0_1100011;//beq if(x4=x5) jump to _rom[33] 
            _rom[20][`MemBus] = 32'b0000000_11100_10010_001_1010_0_1100011;//bne if(x18 != x28) jump to _rom[25]
            _rom[21][`MemBus] = 32'b0000000_00101_11101_000_00101_0110011;//add x5=x5+x29
            _rom[22][`MemBus] = 32'b0100000_11101_00101_000_11101_0110011;//sub x29 = x5-x29
            _rom[23][`MemBus] = 32'b0000000_00110_10010_000_00110_0110011;//add x6=x6+x18
            _rom[24][`MemBus] = 32'b1_1111110100_1_11111111_11111_1101111;//jal jump to _rom[18]
            _rom[25][`MemBus] = 32'b0000000_00101_00010_010_00000_0100011;//sw _ram[6]=x5
            _rom[26][`MemBus] = 32'b000000000000_00001_000_11111_1100111;//jalr jump to _rom[29]
            _rom[27][`MemBus] = 32'b00000000000000000000000000000000;//nop
            _rom[28][`MemBus] = 32'b00000000000000000000000000000000;//nop
            _rom[29][`MemBus] = 32'b00000000000000000000_00101_0110111;//lui x5=0
            _rom[30][`MemBus] = 32'b00_0000_0000_00010_010_00101_0000011;//lw x5=_ram[6]
            _rom[31][`MemBus] = 32'b000000000111_00000_000_00011_0010011;//x3=6
            _rom[32][`MemBus] = 32'b000000000000_00000_000_00000_1110011;//ecall jump to _rom[33]
            _rom[33][`MemBus] = 32'b0000000_00101_10010_000_00101_0110011;//add x5=x5+x18
            _rom[34][`MemBus] = 32'b0_1111111110_0_00000000_11111_1101111;//jal jump to _rom[33]
        end else begin
            data_o = _rom[addr_i[31:2]];
        end
    end

endmodule

